The present invention relates to a semiconductor apparatus, and for example, to a microcomputer.
In general, in a single-chip microcomputer, functional blocks such as a ROM (Read Only Memory) for holding programs, a RAM (Random Access Memory) for holding data, and an input/output circuit for inputting and outputting data or signals are formed on a single semiconductor substrate centering around a CPU (Central Processing Unit). Such single-chip microcomputers are used in various device control.
In device control of the single-chip microcomputer, there is a request for a data transfer in response to an event such as an interruption. Although a CPU can realize arbitrary processing by a combination of instructions, in order to perform interruption processing, it is necessary to execute exception processing, evacuation and recover processing of a stack, and a return instruction in order to switch a flow of processing. In such a case, an operation time of the CPU for reading instructions at the time of the data transfer tends to be long.
In order to solve the above-mentioned problem of a data transfer, there is a technique (Japanese Unexamined Patent Application Publication No. H01-125644) in which a data transfer controller is provided in a single-chip microcomputer, and a data transfer is performed by a small amount of hardware in response to requests from a number of peripheral processing apparatuses (input/output circuits). In this technique, a storage device (RAM) stores data transfer information such as a source address indicating a location in a memory in which data which should be transferred is stored. This technique further provides a vector table that stores an address indicating a location in the storage device (RAM) where all information necessary for the data transfer is stored. Further, means for referring to a content of the vector table in response to a startup request for the data transfer, and means for obtaining all the information necessary for the data transfer from the content of the vector table are provided. Although this technique achieves the data transfer by a small amount of hardware, a content of the data transfer is not taken into account.
Meanwhile, there is a technique (Japanese Unexamined Patent Application Publication No. 5-307516) in which different types of data transfer are performed according to a mode of the data transfer in order to extend an application range of the data transfer in a data transfer controller. This technique suggests a repeat transfer mode and a block transfer mode as the mode of the data transfer. This technique enables control on source and destination addresses and a selection of the number of transfers. For example, when this technique is applied to a system such as a printer, it is possible to control a stepper motor and control print data in the printer. Further, this technique is preferable for accumulating received data in a memory. As this technique holds data transfer information in dedicated hardware inside the data transfer controller and enables a selection of a configuration of the transfer information in a short address mode or a full address mode in order to effectively use the hardware. In this example, in the stepper motor, an amount of movement is proportional to a rotation angle, thus no feedback is necessary, and the stepping motor may only transfer a predetermined number of pieces of data in a predetermined order. In this technique, one of the source address and the destination address will be at, for example, a RAM, however it is not supposed to use the RAM while updating a memory content of the RAM.
There is another technique (Japanese Unexamined Patent Application Publication No. 7-129537) in which information necessary for a data transfer is stored in a storage device, and one operation of a data transfer controller can specify a data transfer of at least one piece of information (a chain transfer or a chain operation). This technique can be applied to various usages as arbitrary number of transfers are enabled by an arbitrary startup cause. It is eventually possible to improve flexibility of the system configuration, thereby improving the usability.
There is another technique (Japanese Unexamined Patent Application Publication No. 2000-194647) in which an arithmetic logic unit capable of performing a comparison between data that is set inside a data transfer controller in advance and data to be transferred and capable of performing a simple calculation is included inside a data transfer controller. In this technique, as the data transfer controller, which is dedicated hardware, performs the data transfer, data transfer that is faster than a CPU can be achieved. It is thus possible to reduce the number of times of interruption processing in the CPU, thereby improving the efficiency of the processing.